library ieee;
use ieee.std_logic_1164.all;

entity Decoder2x4 is
	port (
		a,b : in bit;
		z1, z2, z3, z4 : out bit
	);
end entity Decoder2x4;

architecture DATAFLOW of Decoder2x4 is
    
 	begin
 	    
 	    z1 <= (not a) and (not b);
		z2 <= a and (not b);
		z3 <= (not a) and b;
		z4 <= a and b;
		
end architecture DATAFLOW;

architecture STRUCTURAL of Decoder2x4 is
	
	component and2
	
	port(a,b : in bit;
		z : out bit
	);
	
	end component;
	
	component notDataFlow
	
	port(a : in bit;
		z : out bit
	);
	
	end component;

	for all : and2 use entity work.and2(DATAFLOW); 
	for all : notDataFlow use entity work.notDataFlow(DATAFLOW); 
	
	signal aNot : bit;
	signal bNot : bit;
	
begin

	N1 : notDataFlow port map(a, aNot);
	N2 : notDataFlow port map(b, bNot);
	A1 : and2 port map(aNot, bNot, z1);
	A2 : and2 port map(a, bNot, z2);
	A3 : and2 port map(aNot, b, z3);
	A4 : and2 port map(a, b, z4);

end architecture STRUCTURAL;
